The main difference between simulation and synthesis in VHDL is that simulation is used to verify the functionality of the circuit while synthesis is used to compile VHDL and map into an implementation technology such as FPGA.
Generally, Hardware Description Language (HDL) is a language that describes the functionalities of electronic circuits. These languages are different from regular programming languages. HDL helps to describe digital systems such as microprocessors and flip-flops. VHDL is one popular Hardware Description Language. Overall, VHDL helps to accomplish two goals: simulation and synthesis.
Key Areas Covered
1. What is Simulation in VHDL
– Definition, Functionality
2. What is Synthesis in VHDL
– Definition, Functionality
3. Difference Between Simulation and Synthesis in VHDL
– Comparison of Key Differences
HDL, Simulation, Synthesis, VHDL
What is Simulation in VHDL
Simulation or simulation program in VHDL helps to test the logic design using simulation models to represent the logic circuits that interface to the design. A set of simulation models is a testbench.
VHDL simulator is an event-driven simulator. Therefore, each transaction is added to an event queue for specific scheduling time. Furthermore, the simulation changes between the two modes. They are statement execution and event processing. The statement execution refers to the evaluation of triggered statements, while event processing refers to processing the events in the queue.
What is Synthesis in VHDL
Synthesis is the process of developing a physical system using the abstract descriptions of predefined building blocks such as flipflops, latches and logic gates. It creates a gate-level netlist from a model of a circuit described in VHDL. Finally, the synthesis helps to map VHDL to technologies such as FPGA and ASIC. Most FPGA manufacturers provide free tools to synthesize VHDL to use with their chips.
Synthesis tools mainly focus on the logic design of FPGA and ASIC. They do not consider sensitivity list as they focus on three basic logics: combinational logic, edge sensitive storage (flip flops and some RAM) and level sensitive storage (latches and some RAM).
Moreover, some VHDLs are non-synthesizable. Thus, the programmer can write VHDL code he can simulate but not synthesize. For a design description to be synthesizable, the constructs should be acceptable to the synthesis tool.
Difference Between Simulation and Synthesis in VHDL
Simulation is the process of describing the behaviour of the circuit using input signals, output signals and delays. But, synthesis is the process of constructing a physical system from an abstract description using a predefined set of building blocks. Thus, this describes the fundamental difference between simulation and sensitivity.
Moreover, simulation (simulator) uses the sensitivity list to figure out when to run the process while synthesis ignores the sensitivity list. Hence, this is another difference between simulation and sensitivity.
Above all, the usage contributes to the main difference between simulation and sensitivity. While simulation helps to verify the functionality of the circuit, synthesis helps to convert VHDL descriptions to match the target technology.
In brief, a programmer or electronic designer can use VHDL language to test models to describe logic circuits. Here, the VHDL is involved in accomplishing two major goals; they are the simulation of electronic designs and the synthesis of those designs. The main difference between simulation and synthesis in VHDL is that the simulation is used to verify the functionality of the circuit while synthesis is used to compile VHDL and map into an implementation technology such as FPGA.